MC908KX2MDWE Datasheet, PDF (110/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Input/Output (I/O) Ports (PORTS)
When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 11-2 summarizes the operation of the port B pins.
Table 11-2. Port B Pin Functions
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Accesses to DDRB
Read/Write
0
X
Input, Hi-Z
DDRB7–DDRB0
1
X
Output
X = Don’t care
Hi-Z = High impedance
DDRB7–DDRB0
1. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Write
Pin
PTB7–PTB0⁽¹⁾
PTB7–PTB0
PTB7–PTB0
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
110
Freescale Semiconductor