MC908KX2MDWE Datasheet, PDF (176/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Development Support
NOTE
PTA1 = 0 and PTA0 = 1 allow normal serial communications. PTA1 = 1
allows parallel communications during security code entry. (For parallel
communications, configure PTA0 = 0 or PTA0 = 1.)
The MCU initially comes out of reset using the external clock for its clock source. This overrides the user
mode operation of the oscillator circuits where the part comes up using the internally generated oscillator.
Running from an external clock allows the MCU, using an appropriate frequency clock source, to
communicate with host software at standard baud rates.
NOTE
While the voltage on IRQ1 is at V_TST, the ICG module is bypassed and the
external square-wave clock becomes the clock source. Dropping IRQ1 to
below V_TST will remove the bypass and the MCU will revert to the clock
source selected by the ICG (as determined by the settings in the ICG
registers).
In normal monitor mode with V_TST on IRQ1, the MCU alters
PTB7/(OSC2)/RST to function as a RST pin. This is useful for testing the
MCU. Dropping IRQ1 voltage to below V_TST will revert PTB7/(OSC2)/RST
to its user mode function.
The computer operating properly (COP) module is disabled in normal monitor mode whenever V_TST is
applied to the IRQ1 pin. If the voltage on IRQ1 is less than V_TST, the COP module is controlled by the
COPD configuration bit.
16.3.1.3 Forced Monitor Mode
If the voltage applied to the IRQ1 is less than V_TST, the MCU will come out of reset in user mode. The
MENRST module is monitoring the reset vector fetches and will assert an internal reset if it detects that
the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode
without requiring high voltage on the IRQ1 pin.
Once out of reset, the monitor code is initially executing off the internal clock at its default frequency. The
monitor code reconfigures the ICG module to use the external square-wave clock source. Switching to an
external clock source allows the MCU, using an appropriate clock frequency, to communicate with host
software at standard baud rates.
The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will
automatically force the MCU to come back to the forced monitor mode.
16.3.1.4 Monitor Mode Vectors
Monitor mode uses alternate vectors for reset and SWI interrupts. The alternate vectors are in the $FE
page instead of the $FF page and allow code execution from the internal monitor firmware instead of user
code. Table 16-2 shows vector differences between user mode and monitor mode.
Table 16-2. Monitor Mode Vector Relocation
Modes
User
Monitor
Reset Vector High
$FFFE
$FEFE
Reset Vector Low
$FFFF
$FEFF
SWI Vector High
$FFFC
$FEFC
SWI Vector Low
$FFFD
$FEFD
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
176
Freescale Semiconductor