MC908KX2MDWE Datasheet, PDF (82/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Internal Clock Generator Module (ICG)
period when any of the operating condition changes. This happens whenever the part is reset, the ICG
multiply factor (N) is changed, the ICG trim factor (TRIM) is changed, or the internal clock is enabled after
inactivity (STOP or disabled operation). The time that the ICLK takes to adjust to the correct period is
known as the settling time.
Settling time depends primarily on how many corrections it takes to change the clock period, and the
period of each correction. Since the corrections require four periods of the low-frequency base clock
(4*τ_IBASE), and since ICLK is N (the ICG multiply factor for the desired frequency) times faster than
IBASE, each correction takes 4*N*τ_ICLK. The period of ICLK, however, will vary as the corrections occur.
7.4.6.1 Settling To Within 15%
All FLASH mask sets other than 0K45D, 1K45D, 0L09H, 1L09H have 15% comparators that improve
stability at low temperatures.
When the error is greater than 15%, the filter takes eight corrections to double or halve the clock period.
Due to how the DCO increases or decreases the clock period, the total period of these eight corrections
is approximately 11 times the period of the fastest correction. (If the corrections were perfectly linear, the
total period would be 11.5 times the minimum period; however, the ring must be slightly nonlinear.)
Therefore, the total time it takes to double or halve the clock period is 44*N*t_ICLKFAST.
If the clock period needs more than doubled or halved, the same relationship applies, only for each time
the clock period needs doubled, the total number of cycles doubles. That is, when transitioning from fast
to slow, going from the initial speed to half speed takes 44*N*t_ICLKFAST; from half speed to quarter speed
takes 88*N*t_ICLKFAST; going
series can be expressed as
(f2ro^x-m1)q*4u4a*rNte*rt_I^s_C^p_L^e_K^e_F^d_AS^t_T^{o,ewighhetrhesxpiesetdhetankuems 1b7e6r *oNf *titmIC}e^LKs^Ft^Ah^Se^Ts; paeneddsnoeoend.sThis
doubled or halved. Since 2^x happens to be equal to τ_ICLKSLOW/τ_ICLKFAST, the equation reduces to
44*N*(τ_ICLKSLOW-τ_ICLKFAST).
NOTE
Increasing speed takes much longer than decreasing speed since N is
higher. This can be expressed in terms of the initial clock period (τ₁) minus
the final clock period (τ₂) as such:
τ₁₅ = abs[44N(τ₁ – τ₂)]
Once the clock period is within 15% of the desired clock period, the internal clock stable bit (ICGS) will be
set and the clock frequency is usable, although the error will be as high as 15%.
7.4.6.2 Total Settling Time
Once the clock period is within 15% of the desired clock period, the filter starts making minimum
adjustments. In this mode, each correction will adjust the frequency between 0.202% and 0.368%. A
maximum of 88 corrections will be required to get to the minimum error. Each correction takes
approximately the same period of time, or 4*τ_IBASE. This makes 88 corrections (352*τ_IBASE) to get from
15% to the minimum error. The total time to the minimum error is:
τ_tot = abs[44N(τ₁ – τ₂)] + 352τ_IBASE
The equations for τ₁₅, τ₅, and τ_tot are dependent on the actual initial and final clock periods τ₁ and τ₂, not
the nominal. This means the variability in the ICLK frequency due to process, temperature and voltage
must be considered. Additionally, other process factors and noise can affect the actual tolerances of the
points at which the filter changes modes. This means a worst case adjustment of up to 35% (ICLK clock
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
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Freescale Semiconductor