MC908KX2MDWE Datasheet, PDF (71/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Functional Description
reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these
outputs on the capacitor size, current reference, and voltage reference causes up to ±25% error in f_NOM.
7.3.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock
(ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage
control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG
registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the
low frequency base clock’s period, as shown in Table 7-1. In some extreme error conditions, such as
operating at a V_DD level which is out of specification, the DLF may attempt to use a value above the
maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and
$F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering
from this condition requires subtracting (increasing frequency) in the normal fashion until the value is
again below $9FF (if the desired value is $9xx, the value may settle at $Axx through $Fxx — this is an
acceptable operating condition). If the error is less than ±15%, the ICG’s filter stable indicator (FICGS) is
set, indicating relative frequency accuracy to the clock monitor.
All FLASH mask sets other than 0K45D, 1K45D, 0L09H, 1L09H have 15% comparators that improve
stability at low temperatures.
Table 7-1. Correction Sizes from DLF to DCO
Frequency Error
of IBASE compared
to f_NOM
IBASE < 0.85 f_NOM
0.85 f_NOM < IBASE
IBASE < f_NOM
f_NOM < IBASE
IBASE < 1.15 f_NOM
1.15 f_NOM < IBASE
DDVI[3:0]:DSTG[7:0]
Correction
–32 (–$020)
–1 (–$001)
+1 (+$001)
+32 (+$020)
Current to New
DDIV[3:0]:DSTG[7:0] ⁽¹⁾
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
$xFF to $xDF
$x20 to $x00
$xFF to $xFE
$x01 to $x00
$xFE to $xFF
$x00 to $x01
$xDF to $xFF
$x00 to $x20
Relative Correction
in DCO
–2/31
–2/19
–0.0625/31
–0.0625/17.0625
+0.0625/30.9375
+0.0625/17
+2/29
+2/17
–6.45%
–10.5%
–0.202%
–0.366%
+0.202%
+0.368%
+6.90%
+11.8%
1. x =Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
carries or borrows.
7.3.3 External Clock Generator
The ICG also provides for an external oscillator or external clock source, if desired. The external clock
generator, shown in Figure 7-3, contains an external oscillator amplifier and an external clock input path.
7.3.3.1 External Oscillator Amplifier
The external oscillator amplifier provides the gain required by an external crystal connected in a Pierce
oscillator configuration. The amount of this gain is controlled by the slow external (EXTSLOW) bit in the
CONFIG (or MOR) register. When EXTSLOW is set, the amplifier gain is reduced for operating
low-frequency crystals (32 kHz to 100 kHz). When EXTSLOW is clear, the amplifier gain will be sufficient
for 1 MHz to 8 MHz crystals. EXTSLOW must be configured correctly for the given crystal or the circuit
may not operate.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
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