MC908KX2MDWE Datasheet, PDF (167/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

I/O Registers
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
1
X
X
X
Table 15-3. Mode, Edge, and Level Selection
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Mode
Output preset
Input capture
Output compare
or PWM
Buffered output
compare or
buffered PWM
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the PTAx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1 and clear output on compare is selected, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent. As Figure 15-9 shows, the
CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at 100 percent duty
cycle level until the cycle after CHxMAX is cleared.
NOTE
The PWM 0 percent duty cycle is defined as output low all of the time. To
generate the 0 percent duty cycle, select clear output on compare and then
clear the TOVx bit (CHxMAX = 0). The PWM 100 percent duty cycle is
defined as output high all of the time. To generate the 100 percent duty
cycle, use the CHxMAX bit in the TSCx register.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
167