MC908KX2MDWE Datasheet, PDF (140/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

System Integration Module (SIM)
13.3 Reset and System Initialization
The MCU has these internal reset sources:
• Power-on reset (POR) module
• Computer operating properly (COP) module
• Low-voltage inhibit (LVI) module
• Illegal opcode
• Illegal address
• Forced monitor mode entry reset (MENRST) module
All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
These internal resets clear the SIM counter and set a corresponding bit in the SIM reset status register
(SRSR). See 13.4 SIM Counter and 13.7.1 SIM Reset Status Register.
13.3.1 Active Resets from Internal Sources
An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, POR, or
MENRST as shown in Figure 13-4.
NOTE
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM asserts IRST. The internal reset signal then follows
with the 64-cycle phase as shown in Figure 13-5.
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
MENRST
Figure 13-4. Sources of Internal Reset
IRST
CGMXCLK
IAB
64 CYCLES
Figure 13-5. Internal Reset Timing
VECTOR HIGH
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
140
Freescale Semiconductor