MC908KX2MDWE Datasheet, PDF (49/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Functional Description
Clearing the EXTXTALEN bit (default setting) allows the PTB7/(OSC2)/RST pin to function as a
general-purpose I/O pin. Refer to Table 4-1 for configuration options for the external source. See
Chapter 7 Internal Clock Generator Module (ICG) for a more detailed description of the external clock
operation.
EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the
valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock
monitor will expect an external clock source in the valid range for externally generated clocks when
using the clock monitor (60 Hz to 32 MHz).
EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for
a 4096-cycle timeout to allow the proper stabilization time for a crystal. When EXTXTALEN is clear,
the stabilization divider is configured to 16 cycles since an external clock source does not need a
startup time.
1 = Allows PTB7/(OSC2)/RST to be an external crystal connection.
0 = PTB7/(OSC2)/RST functions as an I/O port pin (default).
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable the internal clock generator module to continue to generate
clocks (either internal, ICLK, or external, ECLK) in stop mode. See Chapter 7 Internal Clock Generator
Module (ICG). This function is used to keep the timebase running while the rest of the microcontroller
stops. See Chapter 14 Timebase Module (TBM). When clear, all clock generation will cease and both
ICLK and ECLK will be forced low during stop mode. The default state for this option is clear, disabling
the ICG in stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
NOTE
This bit has the same functionality as the OSCSTOPENB CONFIG bit in
MC68HC908GP20 and MC68HC908GR8 parts.
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock is used as clock source for SCI.
0 = CGMXCLK is used as clock source for SCI.
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. See Chapter 5 Computer Operating
Properly Module (COP).
1 = COP timeout period = 2¹³ – 2⁴ CGMXCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
49