MC908KX2MDWE Datasheet, PDF (143/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

13.5 Program Exception Control
Normal, sequential program execution can be changed in two ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
Program Exception Control
13.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the return-from-interrupt
(RTI) instruction recovers the CPU register contents from the stack so that normal processing can
resume. Figure 13-7 shows interrupt entry timing. Figure 13-8 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
MODULE
INTERRUPT
I BIT
Figure 13-7. Interrupt Entry
IAB
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
IDB
CCR
A
X PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND
R/W
Figure 13-8. Interrupt Recovery
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. As shown in Figure
13-9, once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of
priority, until the latched interrupt is serviced or the I bit is cleared.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
143