MC908KX2MDWE Datasheet, PDF (144/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

System Integration Module (SIM)
FROM RESET
YES
IIBBIITTSSEETT??
NO
IRQ1
YES
INTERRUPT
?
NO
ICG CLK MON ^YES
INTERRUPT
?
NO
OTHER
YES
INTERRUPTS
?
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
YES
?
NO
RTI
INSTRUCTION
YES
?
NO
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 13-9. Interrupt Processing
13.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
144
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