MC908KX2MDWE Datasheet, PDF (106/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Input/Output (I/O) Ports (PORTS)
11.2 Port A
Port A is a 5-bit special function port on the MC68HC908KX8 that shares all of its pins with the keyboard
interrupt module (KBI) and the 2-channel timer. Port A contains software programmable pullup resistors
enabled when a port pin is used as a general-function input. Port A pins are also high-current port pins
with 15-mA source/15-mA sink capabilities.
11.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the five port A pins.
Address: $0000
Bit 7
6
Read: 0
0
Write:
Reset:
Alternate Function:
5
4
3
2
1
Bit 0
0
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by reset
KBD4
KBD3
KBD2
KBD1
KBD0
Alternate Function:
VREFH TCH1
TCH0
= Unimplemented
Figure 11-2. Port A Data Register (PTA)
PTA4–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBD4–KBD0 — Keyboard Wakeup Bits
The keyboard interrupt enable bits, KBIE4–KBIE0, in the keyboard interrupt control register, enable
the port A pins as external interrupt pins. See Chapter 9 Keyboard Interrupt Module (KBI).
TCH1 and TCH0 — Timer Channel I/O Bits
The PTA3/KBD3/TCH1 and PTA2/KBD2/TCH0 pins are the TIM input capture/output compare pins.
The edge/level select bits, ELSxB and ELSxA, determine whether the pins are timer channel I/O pins
or general-purpose I/O pins. See Chapter 9 Keyboard Interrupt Module (KBI).
11.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Read: 0
0
0
DDRA4 DDRA3 DDRA2 DDRA1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
106
Freescale Semiconductor