MC908KX2MDWE Datasheet, PDF (133/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

I/O Registers
the SCDR. Once cleared, BKF can become set again only after 1s again appear on the RxD pin
followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception-in-Progress Flag Bit
This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search.
RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
12.7.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
Address: $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read: R7
R6
R5
R4
R3
R2
R1
R0
Write: T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 12-16. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits, R7–R0. Writing to address $0018
writes the data to be transmitted, T7–T0. Reset has no effect on the SCI data register.
NOTE
Do not use read-modify-write instructions on the SCI data register.
12.7.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
Address:
Read:
Write:
Reset:
$0019
Bit 7
6
5
4
3
2
1
0
0
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 12-17. SCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
133