MC908KX2MDWE Datasheet, PDF (162/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Timer Interface Module (TIM)
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM
channel 0 registers (TCH0H and TCH0L) initially control the buffered PWM output. TIM status control
register 0 (TSCR0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100
percent duty cycle output. See 15.8.4 TIM Channel Status and Control Registers.
15.5 Interrupts
These TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer overflow flag (TOF) bit is set when the TIM counter reaches
the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt
enable bit, TOIE, enables TIM overflow interrupt requests. TOF and TOIE are in the TIM status and
control registers.
• TIM channel flags (CH1F and CH0F) — The CHxF bit is set when an input capture or output
compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel
x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
15.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
15.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
15.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
15.7 I/O Signals
Port A shares two of its pins with the TIM, PTA3/KBD3/TCH1 and PTA2/KBD2/TCH0. Each channel
input/output (I/O) pin is programmable independently as an input capture pin or an output compare pin.
TCH0 can be configured as buffered output compare or buffered PWM pins.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
162
Freescale Semiconductor