MC908KX2MDWE Datasheet, PDF (88/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Internal Clock Generator Module (ICG)
ICGON — Internal Clock Generator On Bit
This read/write bit enables the internal clock generator. ICGON can be cleared when the CS bit has
been set and the CMON bit has been clear for at least one bus cycle. ICGON is forced set when the
CMON bit is set, the CS bit is clear, or during reset.
1 = Internal clock generator enabled
0 = Internal clock generator disabled
ICGS — Internal Clock Generator Stable Bit
This read-only bit indicates when the internal clock generator has determined that the internal clock
(ICLK) is within about 15% of the desired value. This bit is forced clear when the clock monitor
determines the ICLK is inactive, when ICGON is clear, when the ICG multiplier register (ICGMR) is
written, when the ICG trim register (ICGTR) is written, during STOP with OSCENINSTOP low, or
during reset.
1 = Internal clock is within 15% of the desired value
0 = Internal clock may not be within 15% of the desired value
ECGON — External Clock Generator On Bit
This read/write bit enables the external clock generator. ECGON can be cleared when the CS and
CMON bits have been clear for at least one bus cycle. ECGON is forced set when the CMON bit or the
CS bit is set. ECGON is forced clear during reset.
1 = External clock generator enabled
0 = External clock generator disabled
ECGS — External Clock Generator Stable Bit
This read-only bit indicates when at least 4096 external clock (ECLK) cycles have elapsed since the
external clock generator was enabled. This is not an assurance of the stability of ECLK but is meant
to provide a start-up delay. This bit is forced clear when the clock monitor determines ECLK is inactive,
when ECGON is clear, during STOP with OSCENINSTOP low, or during reset.
1 = 4096 ECLK cycles have elapsed since ECGON was set
0 = External clock is unstable, inactive, or disabled
7.7.2 ICG Multiplier Register
Address: $0037
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
N6
N5
N4
N3
N2
N1
N0
Reset:
0
0
0
1
0
1
0
1
= Unimplemented
Figure 7-12. ICG Multiplier Register (ICGMR)
N6:N0 — ICG Multiplier Factor Bits
These read/write bits change the multiplier used by the internal clock generator. The internal clock
(ICLK) will be (307.2 kHz ± 25%) * N. A value of $00 in this register is interpreted the same as a value
of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal
21) for default frequency of 6.45 MHz ± 25% (1.613 MHz ± 25% bus).
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
88
Freescale Semiconductor