MC908KX2MDWE Datasheet, PDF (102/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Low-Voltage Inhibit (LVI)
Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, V_TRIPF, to be configured
for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, V_TRIPF, to be configured for 3-V
operation. The actual trip thresholds are specified in 17.5 5.0-Vdc DC Electrical Characteristics and .
NOTE
After a power-on reset, the LVI’s default mode of operation is 3 volts. If a
5-V system is used, the user must set the LVI5OR3 bit to raise the trip point
to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset
while the V_DD supply is not above the V_TRIPR for 5-V mode, the MCU will
immediately go into reset. The next time the LVI releases the reset, the
supply will be above the V_TRIPR for 5-V mode.
Once an LVI reset occurs, the MCU remains in reset until V_DD rises above a voltage, V_TRIPR, which
causes the MCU to exit reset. See Chapter 13 System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can monitor V_DD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at 0 to enable the LVI module, and
the LVIRSTD bit must be at 1 to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be at 0 to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF. V_TRIPR is greater than
V_TRIPF by the hysteresis voltage, V_HYS.
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V_TRIPF [5 V] or V_TRIPF [3 V]) may be lower than this. See 17.5
5.0-Vdc DC Electrical Characteristics and for the actual trip point voltages.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
102
Freescale Semiconductor