MC908KX2MDWE Datasheet, PDF (171/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

16.2.1.3 TIM1 and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
Break Module (BRK)
16.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt when BDCOP bit is set in break auxiliary register (BRKAR).
16.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• SIM break status register (SBSR)
• SIM break flag control register (SBFCR)
16.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = When read, break address match
0 = When read, no break address match
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
171