MC908KX2MDWE Datasheet, PDF (125/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

12.7 I/O Registers
These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
I/O Registers
12.7.1 SCI Control Register 1
SCI control register 1 (SCC1):
• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOOPS ENSCI TXINV
M
WAKE
ILTY
PEN
PTY
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 12-10. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must
be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
125