MC908KX2MDWE Datasheet, PDF (146/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

System Integration Module (SIM)
13.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 13-11
shows the timing for wait mode entry.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-11. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset. If the COP disable bit, COPD, in the configuration register is a 0,
then the computer operating properly module (COP) is enabled and remains active in wait mode.
Figure 13-12 and Figure 13-13 show the timing for WAIT recovery.
IAB
$DE0B
$DE0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$DE
EXITSTOPWAIT
Note: EXITSTOPWAIT = CPU interrupt
Figure 13-12. Wait Recovery from Interrupt
IAB
$DE0B
64
CYCLES
RST VCT H RST VCT L
IDB $A6 $A6
$A6
IRST
CGMXCLK
Figure 13-13. Wait Recovery from Internal Reset
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
146
Freescale Semiconductor