MC908KX2MDWE Datasheet, PDF (122/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Serial Communications Interface Module (SCI)
With the misaligned character shown in Figure 12-8, the receiver counts 154 RT cycles at the point
when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
-1---5---4-----^–-----1---4---7-- ^{× 100 = 4.54%}
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 12-8, the receiver counts 170 RT cycles at the point
when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
1----7---0-----–_{-----1---6---3-- × 100 = 4.12%}
170
Fast Data Tolerance
Figure 12-9 shows how much a fast received character can be misaligned without causing a noise
error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit
data samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 12-9. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 12-9, the receiver counts 154 RT cycles at the point
when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is
1----5---4-----–_{-----1---6---0-- × 100 = 3.90%.}
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 12-9, the receiver counts 170 RT cycles at the point
when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
122
Freescale Semiconductor