MC908KX2MDWE Datasheet, PDF (149/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

SIM Registers
13.7.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. The interrupt sources and
the interrupt status register flags that they set are summarized in Table 13-2. The interrupt status registers
can be useful for debugging.
Table 13-2. Interrupt Sources
Source
SWI instruction
IRQ1 pin
ICG clock monitor
TIM channel 0
TIM channel 1
TIM overflow
SCI receiver overrun error
SCI receiver noise error
SCI receiver framing error
SCI receiver parity error
SCI receiver full
SCI receiver idle
SCI transmitter empty
SCI transmission complete
Keyboard pins
ADC conversion complete
Timebase module
Flag
—
IRQF1
CMF
CH0F
CH1F
TOF
OR
NF
FE
PE
SCRF
IDLE
SCTE
TC
KEYF
—
TBIE
Mask⁽¹⁾
—
IMASK1
CMIE
CH0IE
CH1IE
TOIE
ORIE
NEIE
FEIE
PEIE
SCRIE
ILIE
SCTIE
TCIE
IMASKK
AIEN
TBF
INT
Register
Flag
—
IF1
IF2
IF3
IF4
IF5
IF11
IF12
IF13
IF14
IF15
IF16
Priority⁽²⁾
0
1
2
3
4
5
6
7
8
9
10
11
Vector
Address
$FFFC–$FFFD
$FFFA–$FFFB
$FFF8–$FFF9
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFE6–$FFE7
$FFE4–$FFE5
$FFE2–$FFE3
$FFE0–$FFE1
$FFDE–$FFDF
$FFDC–$FFDD
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI
instruction.
2. 0 = highest priority
13.7.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
4
3
2
Read: IF6
IF5
IF4
IF3
IF2
IF1
Write: R
R
R
R
R
R
1
Bit 0
0
0
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 13-17. Interrupt Status Register 1 (INT1)
IF5–IF1 — Interrupt Flags 5, 4, 3, 2, and 1
These flags indicate the presence of interrupt requests from the sources shown in Table 13-2.
1 = Interrupt request present
0 = No interrupt request present
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
149