MC908KX2MDWE Datasheet, PDF (164/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Timer Interface Module (TIM)
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS2–PS0 — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 15-2 shows. Reset clears the PS2–PS0 bits.
Table 15-2. Prescaler Selection
PS2–PS0
000
001
010
011
100
101
110
111
TIM Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
15.8.2 TIM Counter Registers
The two read-only TIM counter registers (TCNTH and TCNTL) contain the high and low bytes of the value
in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a
buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset
clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Register name and address: TCNTH — $0021
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset: 0
0
0
0
0
0
1
Bit 0
9
Bit 8
0
0
Register name and address: TCNTL — $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-6. TIM Counter Registers (TCNTH and TCNTL)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
164
Freescale Semiconductor