MC908KX2MDWE Datasheet, PDF (137/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Chapter 13
System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. The SIM is a system state controller that coordinates the central processor unit (CPU)
and exception timing. Together with the CPU, the SIM controls all microcontroller unit (MCU) activities.
Figure 13-1 is a summary of the SIM input/output (I/O) registers. A block diagram of the SIM is shown in
Figure 13-2.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
SIM Reset Status Register ^{Read: POR}
0
COP
ILOP
ILAD MENRST LVI
0
$FE01
(SRSR) Write:
See page 148. _POR:
1
0
0
0
0
0
0
0
Interrupt Status Register 1 ^{Read: IF6}
IF5
IF4
IF3
IF2
IF1
0
0
$FE04
(INT1) Write: R
R
R
R
R
R
R
R
See page 149. _Reset:
0
0
0
0
0
0
0
0
Interrupt Status Register 2 ^{Read: IF14}
IF13
IF12
IF11
IF10
IF9
IF8
IF7
$FE05
(INT2) Write: R
R
R
R
R
R
R
R
See page 150. _Reset:
0
0
0
0
0
0
0
0
Interrupt Status Register 3 ^{Read: IF22}
IF21
IF20
IF19
IF18
IF17
IF16
IF15
$FE06
(INT3) Write: R
R
R
R
R
R
R
R
See page 150. _Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 13-1. SIM I/O Register Summary
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
137