MC908KX2MDWE Datasheet, PDF (85/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

I/O Registers
7.6.3 Slow External Clock (EXTSLOW)
Slow external clock (EXTSLOW), when set, will decrease the drive strength of the oscillator amplifier,
enabling low-frequency crystal operation (30 kHz–100 kHz) if properly enabled with the external clock
enable (EXTCLKEN) and external crystal enable (EXTXTALEN) bits. When clear, EXTSLOW enables
high-frequency crystal operation (1 MHz to 8 MHz).
EXTSLOW, when set, also configures the clock monitor to expect an external clock source that is slower
than the low-frequency base clock (60 Hz–307.2 kHz). When EXTSLOW is clear, the clock monitor will
expect an external clock faster than the low-frequency base clock (307.2 kHz–32 MHz).
The default state for this option is clear.
7.6.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the ICG to continue to generate clocks
(either CGMXCLK, CGMOUT, or TBMCLK) in stop mode. This function is used to keep the timebase
running while the rest of the microcontroller stops. When OSCENINSTOP is clear, all clock generation
will cease and CGMXCLK, CGMOUT, and TBMCLK will be forced low during stop.
The default state for this option is clear.
7.7 I/O Registers
The ICG contains five registers, summarized in Figure 7-10. These registers are:
• ICG control register
• ICG multiplier register
• ICG trim register
• ICG DCO divider control register
• ICG DCO stage control register
Several of the bits in these registers have interaction where the state of one bit may force another bit to
a particular state or prevent another bit from being set or cleared. A summary of this interaction is shown
in Table 7-5.
Addr.
$0035
$0037
$0038
Register Name
Bit 7
6
5
4
3
2
1
ICG Control Register ^Read: _CMIE
(ICGCR) Write:
CMF
0⁽¹⁾
CMON
CS
ICGON
ICGS
ECGON
See page 87. _Reset:
0
0
0
0
1
0
0
1. See CMF bit description for method of clearing.
ICG Multiplier Register ^Read:
(ICGMR) Write:
See page 88. _Reset:
0
N6
N5
N4
N3
N2
N1
0
0
1
0
1
0
ICG Trim Register ^Read:
(ICGTR) Write:
See page 89. _Reset:
TRIM7
1
TRIM6
0
TRIM5
0
TRIM4
0
TRIM3
0
TRIM2
0
TRIM1
0
= Unimplemented
R
= Reserved U = Unaffected
Figure 7-10. ICG Module I/O Register Summary
Bit 0
ECGS
0
N0
1
TRIM0
0
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
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