MC908KX2MDWE Datasheet, PDF (91/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The external interrupt (IRQ) module provides a maskable interrupt input.
8.2 Features
Features of the IRQ module include:
• A dedicated external interrupt pin (IRQ1)
• IRQ1 interrupt control bits
• Internal pullup resistor
• Hysteresis buffer
• Programmable edge-only or edge- and level-interrupt sensitivity
• Automatic interrupt acknowledge
8.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a central processor unit (CPU) interrupt request.
Figure 8-2 shows the structure of the IRQ module.
Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An interrupt latch remains set until one
of these actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (ISCR). Writing a 1 to the ACK1 bit clears the IRQ1
latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge
and low-level triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1 pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level triggered, the interrupt latch remains set until both
of these occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
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