MC908KX2MDWE Datasheet, PDF (105/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Chapter 11
Input/Output (I/O) Ports (PORTS)
11.1 Introduction
Thirteen bidirectional input/output (I/O) pins form two parallel ports in the 16-pin plastic dual in-line
package (PDIP) and small outline integrated circuit (SOIC) package in the MC68HC908KX8 part. All I/O
pins are programmable as inputs or outputs. Port A has software selectable pullup resistors if the port is
used as a general-function input port.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V_DD or V_SS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
See Figure 11-1 for a summary of the I/O port registers.
Addr.
$0000
$0001
$0004
$0005
$000D
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Port A Data Register ^Read:
0
0
0
PTA4
PTA3
PTA2
PTA1
PTA0
(PTA) Write:
See page 106. _Reset:
Unaffected by reset
Port B Data Register ^Read:
(PTB) Write:
See page 108. _Reset:
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
PTB2
PTB1
PTB0
Data Direction Register A ^Read:
0
0
0
DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
(DDRA) Write:
See page 106. _Reset:
0
0
0
0
0
0
0
0
Data Direction Register B ^Read:
(DDRB) Write:
See page 109. _Reset:
DDRB7
0
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
DDRB1
0
DDRB0
0
Port A Input Pullup Enable ^Read:
0
0
0
PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Register (PTAPUE) Write:
See page 108. _Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-1. I/O Port Register Summary
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
105