MC908KX2MDWE Datasheet, PDF (79/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Usage Notes
start
loop
lda
**
sta
brset
cmpa
bne
;Clock Monitor Enabling Code Example
;This code turns on both clocks, selects the desired
; one, then turns on the Clock Monitor and Interrupts
#$AF
;Mask for CMIE, CMON, ICGON, ICGS, ECGON, ECGS
; If Internal Clock desired, mask is $AF
; If External Clock desired, mask is $BF
; If interrupts not desired mask is $2F int; $3F ext
**
;Other code here, such as writing the COP, since ECGS
; and ICGS may take some time to set.
icgcr
;Try to set CMIE. CMIE wont set until CMON set; CMON
; won’t set until ICGON, ICGS, ECGON, ECGS set.
6,ICGCR,error ;Verify CMF is not set
icgcr
;Check if ECGS set, then CMON set, then CMIE set
loop
;Keep looping until CMIE is set.
Figure 7-9. Code Example for Enabling the Clock Monitor
7.4.3 Using Clock Monitor Interrupts
The clock monitor circuit can be used to recover from perilous situations such as crystal loss. To use the
clock monitor effectively, the following notes should be observed:
• Enable the clock monitor and clock monitor interrupts.
• The first statement in the clock monitor interrupt service routine (CMISR) should be a read to the
ICG control register (ICGCR) to verify the clock monitor flag (CMF) is set. This is also the first step
in clearing the CMF bit.
• The second statement in the CMISR should be a write to the ICGCR to clear the CMF bit (write the
bit low). Writing the bit high will not affect it. This statement does not need to immediately follow
the first, but must be contained in the CMISR.
• The third statement in the CMISR should be to clear the CMON bit. This is required to ensure
proper reconfiguration of the reference dividers. This statement must also be contained in the
CMISR.
• Although the clock monitor can only be enabled when both clocks are stable (ICGS is set or ECGS
is set), it will remain set if one of the clocks goes unstable.
• The clock monitor only works if the external slow (EXTSLOW) bit in the CONFIG (or MOR) register
is set to the correct value.
• The internal and external clocks must both be enabled and running in order to use the clock
monitor.
• When the clock monitor detects inactivity, the inactive clock is automatically deselected and the
active clock selected as the source for CGMXCLK and TBMCLK. The CMISR can use the state of
the CS bit to check which clock is inactive.
• When the clock monitor detects inactivity, the application may have been subjected to extreme
conditions which may have affected other circuits. The CMISR should take any appropriate
precautions.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
79