MC908KX2MDWE Datasheet, PDF (170/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

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IAB15–IAB8
IAB15–IAB0
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BREAK
IAB7–IAB0
Figure 16-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
SIM Break Status Register ^{Read: 0}
0
0
1
0
0
$FE00
(SBSR) Write: R
R
R
R
R
R
See page 172. _{Reset: 0}
0
0
1
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
R
$FE03
Register (SBFCR) Write:
See page 173. _{Reset: 0}
Break Address Register High ^Read: _{Bit 15}
14
13
12
11
10
$FE09
(BRKH) Write:
See page 172. _{Reset: 0}
0
0
0
0
0
Break Address Register Low ^Read: _{Bit 7}
6
5
4
3
2
$FE0A
(BRKL) Write:
See page 172. _{Reset: 0}
0
0
0
0
0
Break Status and Control ^Read: _BRKE
BRKA
0
0
0
0
$FE0B
Register (BRKSCR) Write:
See page 171. _{Reset: 0}
0
0
0
0
0
Break Auxiliary Register ^{Read: 0}
0
0
0
0
0
$FE02
(BRKAR) Write:
See page 173. _{Reset: 0}
0
0
0
0
0
Note: Writing a 0 clears BW.
= Unimplemented
R = Reserved
Figure 16-2. I/O Register Summary
1
Bit 0
BW
0
NOTE
R
0
0
R
R
9
Bit 8
0
0
1
Bit 0
0
0
0
0
0
0
0
BDCOP
0
0
16.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
170
Freescale Semiconductor