MC908KX2MDWE Datasheet, PDF (84/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Internal Clock Generator Module (ICG)
7.5.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG (or MOR) register
determines the behavior of the ICG in stop mode. If OSCENINSTOP is low, the ICG is disabled in stop
and, upon execution of the STOP instruction, all ICG activity will cease and the output clocks (CGMXCLK,
CGMOUT, and TBMCLK) will be held low. Power consumption will be minimal.
If OSCENINSTOP is high, the ICG is enabled in stop and activity will continue. This is useful if the
timebase module (TBM) is required to bring the MCU out of stop mode. ICG interrupts will not bring the
MCU out of stop mode in this case.
During STOP, if OSCENINSTOP is low, several functions in the ICG are affected. The stable bits (ECGS
and ICGS) are cleared, which will enable the external clock stabilization divider upon recovery. The clock
monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE) and clock
monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected.
7.6 CONFIG (or MOR) Register Options
There are four CONFIG (or MOR) register options that affect the functionality of the ICG. These options
are:
• EXTCLKEN (external clock enable)
• EXTXTALEN (external crystal enable)
• EXTSLOW (slow external clock)
• OSCENINSTOP (oscillator enable in stop)
All CONFIG (or MOR) register options will have a default setting.
7.6.1 External Clock Enable (EXTCLKEN)
External clock enable (EXTCLKEN), when set, enables the ECGON bit to be set. ECGON turns on the
external clock input path through the PTB6/(OSC1) pin. When EXTCLKEN is clear, ECGON cannot be
set and PTB6/(OSC1) will always perform the PTB6 function.
The default state for this option is clear.
7.6.2 External Crystal Enable (EXTXTALEN)
External crystal enable (EXTXTALEN), when set, will enable an amplifier to drive the PTB7/(OSC2)/RST
pin from the PTB6/(OSC1) pin. The amplifier will only drive if the external clock enable (EXTCLKEN) bit
and the ECGON bit are also set. If EXTCLKEN or ECGON are clear, PTB7/(OSC2)/RST will perform the
PTB7 function. When EXTXTALEN is clear, PTB7/(OSC2)/RST will always perform the PTB7 function.
EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the valid
range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock monitor
will expect an external clock source in the valid range for externally generated clocks when using the clock
monitor (60 Hz to 32 MHz).
EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for a
4096 cycle time-out to allow the proper stabilization time for a crystal. When EXTXTALEN is clear, the
stabilization divider is configured to 16 cycles since an external clock source does not need a start-up
time.
The default state for this option is clear.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
84
Freescale Semiconductor