MC908KX2MDWE Datasheet, PDF (89/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

7.7.3 ICG Trim Register
I/O Registers
Address: $0038
Read:
Write:
Reset:
Bit 7
TRIM7
1
6
5
TRIM6 TRIM5
0
0
= Unimplemented
4
TRIM4
0
3
TRIM3
0
2
TRIM2
0
1
TRIM1
0
Bit 0
TRIM0
0
Figure 7-13. ICG Trim Register (ICGTR)
TRIM7:TRIM0 — ICG Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved to ±2%. Incrementing this register by one decreases
the frequency by 0.195% of the unadjusted value. Decrementing this register by one increases the
frequency by 0.195%. This register cannot be written when the CMON bit is set. Reset sets these bits
to $80, centering the range of possible adjustment.
7.7.4 ICG DCO Divider Register
Address: $0039
Bit 7
6
5
Read:
Write:
Reset:
0
0
0
= Unimplemented
4
3
2
1
Bit 0
DDIV3 DDIV2 DDIV1 DDIV0
0
U
U
U
U
U = Undefined
Figure 7-14. ICG DCO Divider Control Register (ICGDVR)
DDIV3:DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A–$F are interpreted the same as $9. Since the DCO is active during reset,
reset has no effect on DSTG and the value may vary.
7.7.5 ICG DCO Stage Register
Address: $003A
Read:
Write:
Reset:
Bit 7
DSTG7
R
U
6
5
DSTG6 DSTG5
R
R
U
U
= Unimplemented
4
DSTG4
R
U
R
3
DSTG3
R
U
= Reserved
2
1
DSTG2 DSTG1
R
R
U
U
U = Unaffected
Figure 7-15. ICG DCO Stage Control Register (ICGDSR)
Bit 0
DSTG0
R
U
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
89