MC908KX2MDWE Datasheet, PDF (147/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Low-Power Modes
13.6.2 Stop Mode
In stop mode, the SIM counter is held in reset and the CPU and peripheral clocks are held inactive. If the
OSCENINSTOP bit in the configuration register is not enabled, the SIM also disables the internal clock
generator module outputs (CGMOUT and CGMXCLK).
The CPU and peripheral clocks do not become active until after the stop delay timeout. Stop mode is
exited via an interrupt request from a module that is still active in stop mode or from a system reset.
An interrupt request from a module that is still active in stop mode can cause an exit from stop mode. Stop
recovery time is selectable using the SSREC bit in the configuration register. If SSREC is set, stop
recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. Stacking for interrupts
begins after the selected stop recovery time has elapsed.
When stop mode is exited due to a reset condition, the SIM forces a long stop recovery time of 4096
CGMXCLK cycles.
NOTE
Short stop recovery is ideal for applications using canned oscillators that do
not require long startup times for stop mode. External crystal applications
should use the full stop recovery time by clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 13-14 shows stop mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 13-14. Stop Mode Entry Timing
CGMXCLK
INT
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
Figure 13-15. Stop Mode Recovery from Interrupt
SP – 2
SP – 3
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
147