MC908KX2MDWE Datasheet, PDF (75/210 Pages) Freescale Semiconductor, Inc – High-performance M68HC08 architecture, Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

Functional Description
7.3.4.2 Internal Clock Activity Detector
The internal clock activity detector, shown in Figure 7-5, looks for at least one falling edge on the
low-frequency base clock (IBASE) every time the external reference (EREF) is low. Since EREF is less
than half the frequency of IBASE, this should occur every time. If it does not occur two consecutive times,
the internal clock inactivity indicator (IOFF) is set. IOFF will be cleared the next time there is a falling edge
of IBASE while EREF is low.
The internal clock stable bit (ICGS) is also generated in the internal clock activity detector. ICGS is set
when the internal clock generator’s filter stable signal (FICGS) indicates that IBASE is within about 15%
of the target 307.2 kHz ± 25% for two consecutive measurements. ICGS is cleared when FICGS is clear,
the internal clock generator is turned off or in STOP (ICGEN is clear), or when IOFF is set.
CMON
EREF
IBASE
DLF MEASURE
OUTPUT CLOCK
ICGEN
FICGS
R
D
DFFRS
CK Q
S
CK Q
1/4
R
R
D
Q
DFFRR
CK
R
R
D
Q
DFFRR
CK
R
IOFF
ICGS
NAME
NAME
CONFIGURATION (OR MOR) REGISTER BIT
TOP LEVEL SIGNAL
NAME
NAME
REGISTER BIT
MODULE SIGNAL
Figure 7-5. Internal Clock Activity Detector
7.3.4.3 External Clock Activity Detector
The external clock activity detector, shown in Figure 7-6, looks for at least one falling edge on the external
clock (ECLK) every time the internal reference (IREF) is low. Since IREF is less than half the frequency
of ECLK, this should occur every time. If it does not occur two consecutive times, the external clock
inactivity indicator (EOFF) is set. EOFF will be cleared the next time there is a falling edge of ECLK while
IREF is low.
The external clock stable bit (ECGS) is also generated in the external clock activity detector. ECGS is set
on a falling edge of the external stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the
external clock generator on bit is set or the MCU exits STOP (ECGEN = 1) if the external crystal enable
(EXTXTALEN) in the CONFIG (or MOR) register is set, or 16 cycles when EXTXTALEN is clear. ECGS
is cleared when the external clock generator is turned off or in STOP (ECGEN is clear) or when EOFF is
set.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
75