DS616 Datasheet, PDF (8/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 1: PLBV46 PCI Bridge Interface Design Parameters
Generic Feature / Description Parameter Name
Allowable Values
Bridge Features Parameter Group
G1
Number of IPIF devices
C_IPIFBAR
_NUM
G2
IPIF device 0 BAR
C_IPIFBAR_0
1-6; Parameters listed in this
table corresponding to
unused BARs are ignored,
but must be valid values.
BAR label 0 is the required
bar for all values 1-6 and the
index increments from 0 as
BARs are added
Valid PLB address ^{(1), (4)}
G3
IPIF BAR high address 0 C_IPIF_
Valid PLB address ^{(1), (4)}
HIGHADDR_0
G4
PCI BAR to which IPIF BAR C_IPIFBAR2
0 is mapped unless
PCIBAR_0
C_INCLUDE_BAROFFSET
_REG = 1
Vector of length
C_SPLB_AWIDTH
G5
IPIF BAR 0 memory
designator
G6
IPIF device 1 BAR
C_IPIF_SPACE
TYPE_0
C_IPIFBAR_1
0 = I/O space
1 = Memory space
Valid PLB address ^{(1), (4)}
G7
IPIF BAR high address 1 C_IPIF_
Valid PLB address ^{(1), (4)}
HIGHADDR_1
G8
PCI BAR to which IPIF BAR C_IPIFBAR2
1 is mapped unless
PCIBAR_1
C_INCLUDE_BAROFFSET
_REG = 1
Vector of length
C_SPLB_AWIDTH
G9
IPIF BAR 1 memory
designator
G10 IPIF device 2 BAR
C_IPIF_SPACE
TYPE_1
C_IPIFBAR_2
0 = I/O space
1 = Memory space
Valid PLB address ^{(1), (4)}
G11 IPIF BAR high address 2 C_IPIF_
HIGHADDR_2
Valid PLB address ^{(1), (4)}
G12 PCI BAR to which IPIF BAR C_IPIFBAR2
2 is mapped unless
PCIBAR_2
C_INCLUDE_BAROFFSET
_
REG = 1
Vector of length
C_SPLB_AWIDTH
G13 IPIF BAR 2 memory
designator
C_IPIF_SPACETY 0 = I/O space
PE_2
1 = Memory space
G14 IPIF device 3 BAR
C_IPIFBAR_3
Valid PLB address ^{(1), (4)}
G15 IPIF BAR high
address 3
C_IPIF_
HIGHADDR_3
G16 PCI BAR to which IPIF BAR C_IPIFBAR2
3 is mapped unless
PCIBAR_3
C_INCLUDE_BAROFFSET
_REG = 1.
Valid PLB address ^{(1), (4)}
Vector of length
C_SPLB_AWIDTH
Default Value
6
0xFFFFFFFF
0x00000000
0xFFFFFFFF
1
0xFFFFFFFF
0x00000000
0xFFFFFFFF
1
0xFFFFFFFF
0x00000000
0xFFFFFFFF
1
0xFFFFFFFF
0x00000000
0xFFFFFFFF
VHDL Type
integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
DS616 June 22, 2011
www.xilinx.com
8
Product Specification