DS616 Datasheet, PDF (43/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
• If, during a single or a burst transfer prefetch, a PLB rearbitrate is asserted by the PLB slave, the PLBV46 PCI
Bridge automatically retries the PLB request until it is successful, or the limit of 2028 retries is reached. If the
limit is reached, the PLB Master Read Rearb Timeout interrupt is asserted.
• If a PLB Sl_MRdErr occurs during a single or a burst transfer prefetch, the PCI interrupt is strobed. Sl_MErr
can be asserted due to an address phase timeout or a slave assertion of the error signal.
• If, during a burst transfer prefetch, a PLB slave asserts PLB_MRdBTerm which terminates the PLB burst read,
the PLBV46 PCI Bridge automatically retries the PLB request and attempts to prefetch the parameterized
number of data words or up to the range limit.
• On a burst transfer prefetch, the address will not prefetch beyond the valid range. The IP Master in the bridge
attempts to prefetch the parameterized number of data words from addresses up to the limit of the valid range
which is defined by the PCIBAR length parameter. All transactions on the PLB will be burst reads of the PLB
slave that are terminated by the slave, terminated by the bridge receiving the parameterized number of data
words, or terminated when the last address of the defined range is reached. This response is adopted rather
than a target abort which is an option per PCI specification. Recall that the PCI32 core cannot throttle data as a
target after the first data phase. As data is read by the PCI agent, a disconnect occurs when the FIFO is
emptied.
Table 23 summarizes most PLB slave abnormal conditions in a memory read command and how the response is
translated to the PCI initiator.
Table 23: Response to PCI initiator doing a read of a remote PLB slave that terminates the transfer with an
abnormal condition on PLB bus
Abnormal Condition
Memory Read (single)
Memory Read (burst) or Memory Read
Multiple
SERR
Target abort by PCI32 core, but
completes PLB transaction. Flush FIFOs
and assert PLB-side Read SERR
interrupt.
Target abort byPCI32 core, but terminates
PLB transaction. Flush FIFOs and assert
PLB-side PCI Initiator Read SERR
interrupt.
PERR
PLBV46 PCI Bridge ignores the signal
and continues.
PLBV46 PCI Bridge ignores the signal and
continues.
PLB Rearbitrate
Automatically retries PLB read request
and, if not success full after 2028 retries,
asserts PLB Master Read Rearb Timeout
interrupt.
Automatically retries PLB read request
and, if not success full after 2028 retries,
asserts PLB Master Read Rearb Timeout
interrupt.
PLB Sl_MRdErr (including remote
slave IPIF timeout)
Assert PCI interrupt
Assert PCI interrupt
PLB PLB_MRdBTerm
N/A
Automatically retries PLB read request
and attempts to prefetch all data required.
Address increments beyond valid
N/A
range
Disconnect with data on the last valid
address on the PCI bus.
PCI Initiator Initiates a Write Request to a PLB Slave
This section discusses the operation of a remote PCI initiator asserting the memory write command to write data to
a remote PLB slave. For these transactions, the PCI32 core is the PCI target.
Because all PLB address space must be memory space in the PCI sense, the memory write command is the only
write command from a remote PCI initiator to which the PLBV46 PCI Bridge will respond. The command decode
and number words written dictates whether the PLB write operation is a burst or single. Byte enables are buffered
with data on remote PCI initiator writes to a remote PLB slave, but only transferred for singles because the PLB
write protocol does not support dynamic byte enable. All byte enables must be asserted in multiple data phase
burst transactions. The command I/O write is ignored and the configuration write command is responded to by the
PCI32 core but has limited impact on the PLBV46 PCI Bridge.
DS616 June 22, 2011
www.xilinx.com
43
Product Specification