DS616 Datasheet, PDF (50/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Design Implementation
Design Tools
The PLBV46 PCI Bridge design is implemented using the VHDL. All coding standards and abbreviations specified
in IPSPEC001 Virtex-II Pro Coding Standards and IPSPEC002 Virtex-II Pro Standard Abbreviations have been adhered
to.
Xilinx XST and Synplicity Synplify Pro synthesis tools are used for synthesizing the PLBV46 PCI Bridge. The NGC
format from XST and EDIF netlist output from Synplify Pro are then input to the tool suite for actual device
implementation.
Design Debug
The PLBV46 PCI Bridge has a test vector output (PCI_monitor) to facilitate system debug, such as when adding an
ILA to a system. The test vector allows monitoring the PCI bus and is the output of IO-buffers that are instantiated
in the PCI32 core. PCLK, RCLK, and Bus2PCI_INTR are not included in the test vector because these signals do not
have io-buffers instantiated in the core and are accessible to use directly at the core top-level or above. If the port is
not connected in the EDK tool top-level mhs-file, the wrapper leaves this port open. PCI Bus monitoring test vector
bit definition is listed in Table 28.
Table 28: PCI Bus Monitoring Signals
Bit Index
Signal Name
Instantiated I/O-Buffer
PCI Transaction Control Signals
0
FRAME_N
Yes
1
DEVSEL_N
Yes
2
TRDY_N
Yes
3
IRDY_N
Yes
4
STOP_N
Yes
5
IDSEL
Yes
PCI Interrupt Signals
6
INTR_A
Optional
PCI Error Signals
7
PERR_N
Yes
8
SERR_N
Yes
PCI Arbitration Signals
9
REQ_N
Optional
10
reserved
NA
PCI Address, Datapath, and Command Signals
11
PAR
Yes
12-43
AD[31:0]
Yes
44-47
CBE[3:0]
Yes
Design Verification
The PLBV46 PCI Bridge design is verified according to IPSPEC000 PLBV46 PCI Bridge Verification Plan.
DS616 June 22, 2011
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Product Specification