DS616 Datasheet, PDF (14/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 2: PLBV46 PCI Bridge I/O Signals (Cont’d)
Port
Signal Name
Interface
I/O
Description
P31 Sl_SSize(0:1)
PLB Bus
O
P32 Sl_WrDAck
PLB Bus
O
P33 Sl_WrComp
PLB Bus
O
P34 Sl_WrBTerm
PLB Bus
O
P35 Sl_RdDBus(0:C_SPLB_
DWIDTH-1)
PLB Bus
O
P36 Sl_RdDAck
PLB Bus
O
P37 Sl_RdComp
PLB Bus
O
P38 Sl_RdBTerm
PLB Bus
O
P39 Sl_rdWdAddr(0:3)
PLB Bus
O
P40 Sl_MBusy(0:C_SPLB_NUM_ PLB Bus
O
MASTERS-1)
P41 Sl_MRdErr(0:C_SPLB_NUM PLB Bus
O
_MASTERS-1)
P42 Sl_MWrErr(0:C_SPLB_NUM PLB Bus
O
_MASTERS-1)
P43 Sl_MIRQ(0:C_SPLB_NUM_ PLB Bus
O
MASTERS-1)
Table note 1 applies from P43 to P4.
PLB Signals (Master)
P44 MPLB_Clk
PLB Bus
I PLB master bus clock. See table note 1.
P45 MPLB_Rst
PLB Bus
I PLB master bus reset. See table note 1.
P46 PLB_MAddrAck
PLB Bus
I
Table note 1 applies from P46 to P75.
P47 PLB_MSSize(0:1)
PLB Bus
I
P48 PLB_MRearbitrate
PLB Bus
I
P49 PLB_MTimeout
PLB Bus
I
P50 PLB_MWrDAck
PLB Bus
I
P51 PLB_MWrBTerm
PLB Bus
I
P52 PLB_MRdDBus(0:C_MPLB_ PLB Bus
I
DWIDTH-1)
P53 PLB_MRdWdAddr(0:3)
PLB Bus
I
P54 PLB_MRdDAck
PLB Bus
I
P55 PLB_MRdBTerm
PLB Bus
I
P56 PLB_MBusy
PLB Bus
I
P57 PLB_MRdErr
PLB Bus
I
P58 PLB_MWrErr
PLB Bus
I
P59 PLB_MIRQ
PLB Bus
I
P60 M_Request
PLB Bus
O
P61 M_Abort
PLB Bus
O
P62 M_Priority
PLB Bus
O
P63 M_Buslock
PLB Bus
O
DS616 June 22, 2011
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14
Product Specification