DS616 Datasheet, PDF (35/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
For all the transactions listed previously, these design requirements are specified:
• Both PCI and PLB clocks are independent global buffers. For Virtex®-4 or Virtex-5 FPGAs, RCLK must also be
driven by a global buffer.
• The PLB clock can be slower or faster than the PCI clock. The ratio of (PLB clock) / (PCI clock) is limited to
100/15 = 6.67, for example, if LB clock = 100 MHz, the PCI clock must be no less than 15 MHz. For Virtex-4 or
Virtex-5 FPGAs, RCLK must be 200 MHz.
• Address space on the PCI side accessible from the PLB side must be translated to a 2^N contiguous block on the
PLB side. Up to six independent blocks are possible. Each block has parameters for base address (BAR), high
address which must define a 2^N range, address translation vector, and memory designator (memory or I/O).
• All address space on the PLB side that is accessible from the PCI side must be translated to a maximum of three
2^N contiguous blocks on the PCI side. Up to three independent blocks are possible because the PCI32 core
supports up to 3 BARs. Each block has parameters for length which must be a 2^N range, and address
translation vector. Only memory space in the sense of PCI memory space is supported. Space type is mirrored
in the PCI configuration registers.
• Address translations in both directions are performed by high-order address bits substitution in the address
vector before crossing to the other bus domain. Byte addressing integrity is maintained between buses.
• The user’s system must be designed to accommodate certain restrictions on throttling by the PLBV46 PCI
Bridge. Both PLB and PCI burst transactions can be broken up into multiple transactions on the target or slave
bus due to restrictions on bus protocol and modules in the PLBV46 PCI Bridge. Additional PLB and PCI
transactions are automatically initiated when needed to complete a transaction. The first restriction is that the
PCI32 core does not permit throttling of data as either the initiator or target except for insertion of wait states
prior to the first data transfer. Another restriction is, that as a master on the PLB, the PLBV46 PCI Bridge is not
allowed to throttle, but the PCI remote initiator can cause the need to throttle on the PLB. This is particularly
true when the PCI clock is significantly slower than the PLB clock. The PLBV46 PCI Bridge circumvents the
throttling limitations by terminating transactions as needed and reinitiating the request to continue as needed.
Parameters allow the user to optimize the burst size for high data throughput and minimizing the number of
transactions needed to complete the desired burst transactions.
• The interrupt status register in the IPIF contains information to identify an error conditions during the
implementation of the PLBV46 PCI Bridge and the troubleshooting of the system. To clear the interrupt
register bits that were set with an error condition, a write of a "1" to the bit position corresponding to the
operation must be performed.
• The PCI32 core does not permit throttling of data at either the initiator or target except for insertion of wait
states prior to the first data transfer. Consequently, if the PLB device requires throttling that affects the PCI
transaction, the PLBV46 PCI Bridge must terminate the transaction. If the PCI32 core is the initiator, a new PCI
transaction must be initiated to continue data transfer. Although PLB masters are not allowed to throttle data
flow, the combined IPIF and PLBV46 PCI Bridge operation can result in the need for throttling data on the PCI
bus, especially when the PLB clock is slower than the PCI clock. The PLBV46 PCI Bridge handles throttling by
terminating initiator transactions as needed and continuing the PLB master request with a new PCI
transaction. Similarly, new PLB transactions are automatically initiated when needed to complete a PCI
initiator transaction.
DS616 June 22, 2011
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Product Specification