DS616 Datasheet, PDF (45/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
• If during a write command a PLB slave asserts PLB_MWrBTerm which terminates the PLB burst write, the
PLBV46 PCI Bridge automatically retries the PLB request and attempts to empty the fifo. The behavior is the
same as that described for the PLB rearbitrate previously.
• If a PLB Sl_MWrErr occurs while data from the write buffer is being written to a PLB slave, the IP Master will
abort the PLB transaction. When this occurs, the PLBV46 PCI Bridge strobes the PCI interrupt. Sl_MWrErr can
be asserted due to an address phase timeout or a slave assertion of the error signal. Data in the write buffer is
flushed when the PCI interrupt is strobed.
• If on a write command transaction the PCI initiator attempts to go beyond the valid address range, the PLBV46
PCI Bridge does not accept data beyond the valid range. Only valid data is buffered in the bridge and all
buffered data is transferred to the PLB slave. This is adopted rather than a target abort. Due to pipelining in the
PCI32 core, disconnect without data can occur if the initiator is throttling the data when the first address is
near the end of the valid range.
Table 24 summarizes most abnormal conditions that a PLB slave can respond with to a memory write command
and how the response is translated to the PCI initiator.
Table 24: Response to PCI initiator doing a write to a remote PLB slave that terminates the transfer with an
abnormal condition on a bus
Abnormal Condition
Memory Write
Parity Error on Address phase
PCI32 core dictates response with target abort or not accepting
transaction. SERR_N is asserted if enabled
SERR on data phase
Disconnect with data for burst transfers and assert PLB-side PCI Initiator
Write SERR interrupt
PERR on data phase
Disconnect with data for burst transfers and terminate PLB transfer
PLB Rearbitrate
Automatically retried and, if not success full after 2028 retries, asserts PLB
Master Write Rearb Timeout interrupt.
PLB Sl_MWrErr
Disconnect with data if PCI transfer is in progress, flush FIFO, and strobed
the PCI interrupt
PLB_MWrBTerm asserted
Automatically retried until successful.
Address increments beyond valid range
Accept data from only valid address on the PCI bus.
Disconnect to terminate the PCI transaction.
Configuration Transactions
Functionality for host bridge configuration of PCI agents can be implemented in the PLBV46 PCI Bridge at build
time by setting C_INCLUDE_PCI_CONFIG=1. When the bridge is not configured with host bridge configuration
functionality, IDSEL of the PCI32 core is connected to the IDSEL port of the bridge. When the bridge is configured
with host bridge configuration functionality, IDSEL of the PCI32 core is connected internally to the specified
address signal (as described in the next paragraphs) and the IDSEL port of the bridge is not used. As with Memory
and I/O data transactions, byte addressing integrity is maintained in configuration transfers across the bus.
When host bridge configuration functionality is implemented in the PLBV46 PCI Bridge, the PCI32 core in the
PLBV46 PCI Bridge must be configured first. The minimum that must be set is the Bus master enable bit in the
command register and the latency timer register. This requirement is because the PCI32 core has the capability to
configure only itself until the Bus master enable bit is set in the command register of the PCI32 core and the latency
timer register is properly set to avoid timeouts. If the PCI32 core latency timer is set to 0 value, configuration writes
to remote PCI devices do not complete and configuration reads of remote PCI devices will terminate due to the
latency timer expiration. Configuration reads of remote PCI devices with the latency timer set to 0 will return
0xFFFFFFFF.
DS616 June 22, 2011
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Product Specification