DS616 Datasheet, PDF (26/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Global Interrupt Enable Register Description
A global enable is provided to globally enable or disable interrupts from the PCI device. This bit is AND’d with the
output to the interrupt controller. Bit assignment is shown in Table 11. Unlike most other registers, this bit is the
MSB on the PLB. This bit is read/write and cleared upon reset.
Table 11: Global Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access Reset Value
Description
0
Interrupt Global Read/Write
Enable
1-31
Read
0x0
Interrupt Global Enable- PLB bit (0) is the Interrupt Global
Enable bit. Enables all individually enabled interrupts to be
passed to the interrupt controller.
• 0 - Not enabled
• 1 - Enabled
0x0
Unassigned-
Bridge Interrupt Register Description
The PLBV46 PCI Bridge has twelve interrupt conditions. The Bridge Interrupt Enable Register enables each
interrupt independently. Bit assignment in the Interrupt register for a 32-bit data bus is shown in Table 12. The
interrupt register is read-only and bits are cleared by writing a 1 to the bit(s) that are set (1). However, writing a 1 to
any bit(s) that are cleared (0) will toggle them to be set (1). All bits are cleared upon reset. For more information, see
the PLBV46 IPIF Interrupt Product Specification; the module is labeled PLB Interrupt module, but is used in the
PLBV46 IPIF.
Table 12: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus)
Bit(s)
Name
Access
Reset
Value
Description
0-14
15
PLB Read Slave
BAR Overrun
Read
Read/Write 1
to toggle
0x0 Unassigned
0x0 PLB Read Slave BAR Overrun- Interrupt(15) indicates the bridge
PLB Slave was requested to burst past the BAR limit on a read
operation.
16 PLB Write Slave Read/Write 1
BAR Overrun
to toggle
0x0 PLB Write Slave BAR Overrun- Interrupt(16) indicates the bridge
PLB Slave was requested to burst past the BAR limit on a write
operation.
17 PLB Master Read Read/Write 1
Rearb Timeout
to toggle
18 PLB Master Write Read/Write 1
Rearb Timeout
to toggle
19 PCI Initiator Write Read/Write 1
SERR
to toggle
20 PCI Initiator Read Read/Write 1
SERR
to toggle
0x0 PLB Master Read Rearb Timeout- Interrupt(17) indicates the
bridge PLB Master was rearbitrated 2048 times on a read operation.
0x0 PLB Master Write Rearb Timeout- Interrupt(18) indicates the
bridge PLB Master was rearbitrated 2048 times on a write
operation.
0x0 PCI Initiator Write SERR- Interrupt(19) indicates a SERR error
was detected during a PCI initiator write of data to a PLB slave.
0x0 PCI Initiator Read SERR- Interrupt(20) indicates a SERR error was
detected during a PCI initiator read of data from a PLB slave.
21 PLB Master
Read/Write 1
Prefetch Timeout to toggle
0x0 PLB Master Prefetch Timeout- Interrupt(21) indicates the PLB
Discard timer has timed out, which means the prefetched data was
never requested again after the prefetch operation was complete.
22 PLB Master Write Read/Write 1
Retry Timeout
to toggle
0x0 PLB Master Burst Write Retry Timeout- Interrupt(22) indicates
the automatic PCI write retries were not successful due to a latency
timeout on the last retry during a PLB Master burst write to a PCI
target.
DS616 June 22, 2011
www.xilinx.com
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Product Specification