DS616 Datasheet, PDF (36/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
PLB Master Initiates a Read Request of a PCI Target
This section discusses the operation of a PLB master initiating single, burst and cacheline reads of a remote PCI
target. Cacheline reads return the data sequentially, starting at the first word of the line. In these transactions, the
PCI32 core is the PCI initiator.
The operation is similar whether the PCI space is memory or I/O space with the exception of the command sent to
the PCI32 core. A parameter associated with each BAR must be consistent with the remote PCI device memory type
as either I/O or memory. Based on this parameter setting, either I/O or memory commands are asserted. The
PLBV46 IPIF and bridge can accept both fixed length and arbitrary length burst transactions on the PLB, such as
when burst length is determined by the PLB_rdBurst signal. Only one PLB master read of a PCI target is supported
at a time.
Commands supported in PLB master read operations are I/O read, memory read, and memory read multiple. The
command used is based on the address and qualifier decode, which includes the address, memory type, such as I/O
or memory type, and if burst is asserted. Table 19 shows translations of PLB transactions to PCI commands.
The address presented on the PLB is translated to the PCI address space by high-order bit substitution with the 2
lsbs set as follows:
• If the target PCI address space is memory space, the 2 LSBs are set to 00, as in the linear incrementing mode.
• If the PCI target address space is IO-space, the 2 LSBs are passed unchanged from that presented on the PLB
bus.
When the PLBV46 PCI Bridge decodes a PLB read that is for a remote PCI Target, the transfer is rearbitrated on the
PLB bus until the requested data has been prefetched from the remote PCI Target.
If the PLB transaction is not a burst, as when PLB_rdBurst is not high) a single PCI transaction (I/O or Memory
Read command) is performed. After this transaction is successfully completed, a subsequent PLB single read with
the same PLB address and qualifiers then completes on the PLB bus. If the transaction is a PLB burst transaction, as
when PLB_rdBurst is high, and the space type is memory, the PLBV46 PCI Bridge issues a memory read multiple
command on the PCI bus. After this transaction is successfully completed, a subsequent PLB burst read with the
same PLB address and qualifiers then completes on the PLB bus. The number of 32-bit data words read from the
remote PCI Target is determined by the encoded length specified in the PLB fixed-length burst transfer. A Discard
Timer is used to determine how long the PLBV46 PCI Bridge should wait for a subsequent PLB read with the same
PLB address and qualifiers before discarding the prefetched data in the FIFO.
Dynamic byte enable is not supported in Xilinx PLB burst operations and is not supported in the PLB Master read
of a PCI target.All byte enable bits are asserted in PLB master burst read operations.
To comply with the PCI specification, PLB masters are required to re-issue commands when a PCI retry is asserted.
PCI retries are communicated to the PLB master by asserting PLB rearbitrate without an interrupt.
It is the responsibility of the master to properly read data from non-prefetchable PCI targets. For example, the
master must perform single transaction reads of non-prefetchable PCI targets to avoid destructive read operations
of a PCI target.
DS616 June 22, 2011
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Product Specification