DS616 Datasheet, PDF (3/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
• Registers include
• Interrupt and interrupt enable registers at different hierarchal levels
• Reset
• Configuration Address Port, Configuration Data Port and Bus Number/Subordinate Bus Number
• High-order bits for PLB to PCI address translation
• Bridge Device number on PCI bus
• PLB-side Interrupts include
• PLB Master Read SERR and PERR
• PLB Master Read Target Abort
• PLB Master Write SERR and PERR
• PLB Master Write Target Abort
• PLB Master Write Master Abort
• PLB Master Burst Write Retry and Retry Disconnect
• PLB Master Burst Write Retry Timeout
• PCI Initiator Read and Write SERR
• PLB Master Prefetch Timeout
• PLB Master Write Rearb Timeout
• PLB Master Read Rearb Timeout
• Asynchronous FIFOs with burst transfer support and backup capability for retrying transfers as needed. The
maximum burst size on either the PCI or PLB is limited to the usable FIFO depth which is the physical depth-3
• Synchronization circuits for signals that cross time-domain boundaries
• Responds to the PCI latency timer
• Completes posted write operations prior to initiating new operations
• Signal set required for integrating a PCI bus arbiter in the FPGA with the PLBV46 PCI Bridge is available at the
top-level of the PLBV46 PCI Bridge module. The signal set includes PCLK, RST_N, FRAME_I, REQ_N_toArb
and IRDY_I
• Supports PCI clock generated in FPGA
• Parameterized control of I/O-buffer insertion of INTR_A and REQ_N IO-buffers
• All address translations performed by high-order bit substitution. The number of bits substituted depends on
the address range
• Parameterized selection of IPIF BAR high-order bits defined by programmable registers for dynamic
translation operation or by parameters for reduced resource utilization
• Parameterized selection of device ID number (when configuration functionality is included) defined by a
programmable register for dynamic device number definition or by parameter to reduce resource utilization
• The PLBV46 PCI Bridge does not have an integral DMA
• Input signal to provide the means to asynchronous assert INTR_A from a user supplied register. such as the
PLB GPIO register. The signal is Bus2PCI_INTR is an active high signal
• PCI Monitor output port to monitor PCI bus activity
System Reset
When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock
periods of the slowest clock.
DS616 June 22, 2011
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Product Specification