DS616 Datasheet, PDF (13/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
PLBV46 PCI Bus Interface I/O Signals
The I/O signals for the PLBV46 PCI Bridge are listed in Table 2. The interfaces referenced in this table are shown in
Figure 1 in the PLBV46 PCI Bridge block diagram.
Table 2: PLBV46 PCI Bridge I/O Signals
Port
Signal Name
Interface
I/O
Description
System Signals
P1 IP2INTC_Irpt
Internal
O Interrupt from IP to the Interrupt Controller
PLB Signals (Slave)
P2 SPLB_Clk
PLB Bus
I PLB slave bus clock. See table note 1.
P3 SPLB_Rst
PLB Bus
I PLB slave bus reset. See table note 1.
P4 PLB_Abort
PLB Bus
I Note 1 applies from P4 to P43.
P5 PLB_PAValid
PLB Bus
I
P6 PLB_SAValid
PLB Bus
I
P7 PLB_ABus(0:C_SPLB_
AWIDTH-1)
PLB Bus
I
P8 PLB_UABus(0:C_SPLB_
AWIDTH-1)
PLB Bus
I
P9 PLB_RNW
PLB Bus
I
P10 PLB_BE(0:[C_SPLB_
DWIDTH/8]-1)
PLB Bus
I
P11 PLB_Type(0:2)
PLB Bus
I
P12 PLB_Size(0:3)
PLB Bus
I
P13 PLB_MasterID(0:C_SPLB_
PLB Bus
I
MID_WIDTH-1)
P14 PLB_MSize(0:1)
PLB Bus
I
P15 PLB_BusLock
PLB Bus
I
P16 PLB_LockErr
PLB Bus
P17 PLB_TAttribute(0:15)
PLB Bus
P18 PLB_RdBurst
PLB Bus
I
P19 PLB_WrBurst
PLB Bus
I
P20 PLB_WrDBus(0:C_SPLB_
PLB Bus
I
DWIDTH-1)
P21 PLB_RdPrim
PLB Bus
I
P22 PLB_WrPrim
PLB Bus
I
P23 PLB_RdPendPri(0:1)
PLB Bus
I
P24 PLB_WrPendPri(0:1)
PLB Bus
I
P25 PLB_RdPendReq
PLB Bus
I
P26 PLB_WrPendReq
PLB Bus
I
P27 PLB_ReqPri(0:1)
PLB Bus
I
P28 Sl_AddAck
PLB Bus
O
P29 Sl_Wait
PLB Bus
O
P30 Sl_Rearbitrate
PLB Bus
O
DS616 June 22, 2011
www.xilinx.com
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Product Specification