English
Language : 

DS616 Datasheet, PDF (54/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full
LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
It turns out that the number of signals in the PCI protocol requires at least two IDELAYCTRL primitives when
implemented in the Virtex-4 or Virtex-5 architecture. The actual number depends on the pinout defined by the user.
To avoid the undesirable results noted previously, the PCI32 core stand-alone core is fixed to use two IDELAYCTRL
instantiations and prescribes pinouts that require only two IDELAYCTRL primitives. To provide more flexibility to
the user, the PLBV46 PCI Bridge allows specifying the number of IDELAYCTRL primitives from two to six; this is
set at build time by set the parameter C_NUM_IDELAYCTRL.
However, it might be difficult to meet timing when the pinout is spread out to require four to six IDELAYCTRL
primitives and it is recommended to use a PCI pinout packed together enough to require only two IDELAYCTRL
primitives. See the Virtex-4 User Guide discussion of IDELAYCTRL usage and design guidance or the Virtex-4 Library
Guide for IDELAYCTRL primitives for more details.
When more than one IDELAYCTRL is instantiated, the ISE 8.1 tools require LOC constraints on each IDELAYCTRL
instantiation. A failure in MAP occurs if the LOC constraints are not provided. The FPGA Editor tool can be helpful
to determine IDELAYCTRL LOC coordinates for the user's pinout. The syntax for the UCF LOC constraints is
shown in the following example where the instance name in the PLBV46 PCI Bridge for each IDELAYCTRL is
XPCI_IDC0 to XPCI_IDCN where N is the C_NUM_IDELAYCTRL-1. The user need only include an LOC entry for
each instance used in the system design and not for all possible six IDELAY controllers. For each entry, include the
LOC coordinates for the part and pinout in the design. The following example is for a design that uses 2
IDELAYCTRL primitives.
This approach allows users to use the constraint LOC coordinates directly from the PCI32 core ucf-generator. The
UCF generator prescribes I/O pin layout that only uses two IDELAYCTRL primitives. The following example is for
a system with two IDELAYCTRL primitives with example only coordinates. Depending on the user’s pinout, more
IDELAYCTRLs might be needed.
INST *XPCI_IDC0 LOC=IDELAYCTRL_X2Y5;
INST *XPCI_IDC1 LOC=IDELAYCTRL_X2Y6;
An optional method for setting of LOC constraints is to use the C_IDELAYCTRL_LOC parameter. This parameter,
when properly set, generates constraints in the bridge core UCF that is combined with the plbv46_pci bridge NGC
file during normal EDK tool flow. If the LOC constraints are set in the system top-level UCF, this parameter has no
effect for either case of it being properly set or set to default (NOT_SET).
This is because the system top-level UCF overrides all core level ucf constraints. However, if it is not set, then a
warning that it is not set is asserted early in the EDK tool flow for the tool options, generate netlist, generate
bitstream, and other tool options that would invoke synthesis of the plbv46_pci bridge.
If the system top-level UCF does include the LOC constraints, then this warning can be ignored. With EDK 8.1 tools,
MAP will fail if the LOC coordinates are not provided by at least one of the methods. An example of the syntax for
the C_IDELAYCTRL_LOC parameter is shown in the example that follows.
The parameter C_IDELAYCTRL_LOC has the syntax of IDELAYCTRL_XNYM where N and M are coordinates and
multiple entries are concatenated by "-" (dash). The order of entries correspond to IDELAYCNTRL instance names
XPCI_IDC0, XPCI_IDC1, ... up to the maximum index of IDELAY controller instances in the user’s board design.
The maximum index is C_NUM_IDELAYCTRL-1. To use the parameter to set the LOC constraint in the core level
UCF for the above example, the parameter should be set in the MHS-file as shown this example.
PARAMETER C_IDELAYCTRL_LOC="IDELAYCTRL_X2Y5-IDELAYCTRL_X2Y6"
The quotes are optional. The actual number of IDELAYCTRL primitives and corresponding LOC constraints
depends on the user’s PCI pinout and part used.
DS616 June 22, 2011
www.xilinx.com
54
Product Specification