DS616 Datasheet, PDF (15/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 2: PLBV46 PCI Bridge I/O Signals (Cont’d)
Port
Signal Name
Interface
I/O
Description
P64 M_LockErr
PLB Bus
O
P65 M_TAttribute(0:15)
PLB Bus
O
P66 M_Type(0:2)
PLB Bus
O
P67 M_BE(0:[C_MPLB_
DWIDTH/8]-1)
PLB Bus
O
P68 M_RNW
PLB Bus
O
P69 M_UABus(0:C_MPLB_
AWIDTH-1)
PLB Bus
O
P70 M_ABus(0:C_MPLB_
AWIDTH-1)
PLB Bus
O
P71 M_MSize(0:1)
PLB Bus
O
P72 M_size(0:3)
PLB Bus
O
P73 M_RdBurst
PLB Bus
O
P74 M_WrBurst
PLB Bus
O
P75 M_WrDBus(0:C_MPLB_
DWIDTH-1)
PLB Bus
O
Table note 1 applies from P75 to P46.
PCI Address and Datapath Signals
P76 AD[C_PCI_DBUS_
WIDTH-1:0]
PCI Bus
I/O Time-multiplexed address and data bus
P77 CBE[(C_PCI_DBUS_
WIDTH/8)-1:0]
PCI Bus
I/O Time-multiplexed bus command and byte enable bus
P78 PAR
PCI Bus
I/O Generates and checks even parity across AD and CBE
PCI Transaction Control Signals
P79 FRAME_N
PCI Bus
I/O Driven by an initiator to indicate a bus transaction
P80 DEVSEL_N
PCI Bus
I/O Indicates that a target has decoded the address presented
during the address phase and is claiming the transaction
P81 TRDY_N
PCI Bus
I/O Indicates that the target is ready to complete the current data
phase
P82 IRDY_N
PCI Bus
I/O Indicates that the initiator is ready to complete the current
data phase
P83 STOP_N
PCI Bus
I/O Indicates that the target has requested to stop the current
transaction
P84 IDSEL
PCI Bus
I Indicates that the interface is the target of a configuration
cycle
PCI Interrupt Signals
P85 INTR_A
PCI Bus
O Indicates that PCI32 interface requests an interrupt
PCI Error Signals
P86 PERR_N
PCI Bus
I/O Indicates that a parity error was detected while the PCI32
interface was the target of a write transfer or the initiator of a
read transfer
P87 SERR_N
PCI Bus
I/O Indicates that a parity error was detected during an address
cycle, except during special cycles
DS616 June 22, 2011
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Product Specification