DS616 Datasheet, PDF (19/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 3: PLBV46 PCI Bridge Parameters-Port Dependencies (Cont’d)
Generic
Parameter
Affects
Depends
Description
G37 C_INCLUDE_INTR_A_
P63
BUF
If G37 = 0, an io-buffer for P63 is not explicitly
instantiated
G38 C_INCLUDE_REQ_N_BUF
P66
If G38 = 0, an io-buffer for P66 is not explicitly
instantiated
G39 C_TRIG_IPIF_WRBURST_OC
C_LEVEL
G35
Must be set to 2 to the lesser of 24 or the
PCI2IPIF FIFO DEPTH-1 where the PCI2IPIF
FIFO-1 depth is given by 2^G35
G40 C_TRIG_PCI_DATA_XFER_
OCC_LEVEL
G36
Must be set to 2 to the lesser of 24 or the
IPIF2PCI FIFO DEPTH-3 where IPIF2PCI
FIFO DEPTH given by 2^G36
G41 C_NUM_PCI_RETRIES_IN_
WRITES
G42 C_NUM_PCI_PRDS_BETWN_
RETRIES_IN_WRITES
G43 C_BASEADDR
G44
G44
G43 to G44 define range in PLB-memory
space that is responded to by PLBV46 PCI
Bridge register address space
G44 C_HIGHADDR
G43
G43
G43 to G44 define range in PLB-memory
space that is responded to by PLBV46 PCI
Bridge register address space
G45 C_INCLUDE_BAROFFSET_ G4, G8, G12,
G1
If G45=1, G4, G8, G12, G16, G20 and G24
REG
G16, G20
have no meaning. The number of registers
and G24
included is set by G1
G46 C_INCLUDE_DEVNUM_REG
G63
G61, G62 If G61=0, G46 has no meaning. If G46 and
G61=1, G63 has no meaning. Meaningful bits
in the Device Number register are defined by
G62
G47 C_PCI_INIT_RD_BURST_
LENGTH
G48 C_PCI_DISCARD_TIMER
G49 C_PLB_DISCARD_TIMER
G50 C_NUM_IDELAYCTRL
G72
If G72 ≠ Virtex-4 or Virtex-5 FPGA, G50 has no
meaning
G51 C_INCLUDE_GNT_DELAY
G72
If G72 ≠ Virtex-4 or Virtex-5 FPGA, G51 has no
meaning
G52 C_IDELAYCTRL_LOC
G50 and G72
If G72 ≠ Virtex-4 or Virtex-5 FPGA, G52 has no
meaning. If G72=Virtex-4 or Virtex-5 FPGA,
G52 must include the number of LOC
coordinates specified by G50
PCI32 Core Parameters Group
G53 C_DEVICE_ID
G54 C_VENDOR_ID
G55 C_CLASS_CODE
G56 C_REV_ID
G57 C_SUBSYSTEM_ID
G58 C_SUBSYSTEM_VENDOR_ID
G59 C_MAX_LAT
DS616 June 22, 2011
www.xilinx.com
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Product Specification