DS616 Datasheet, PDF (39/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
The address presented on the PLB is translated to the PCI address space by high-order bit substitution with the 2
LSBs set as follows. If the target PCI address space is memory space, the 2 LSBs are set to 00, as in the linear
incrementing mode. If the PCI target address space is IO-space, the 2 LSBs are passed unchanged from that
presented on the PLB bus.
Both single and burst write transfers are posted so the data is buffered in the IPIF2PCI FIFO, which has a depth
defined by the parameter C_IPIF2PCI_FIFO_ABUS_WIDTH. Due to the FIFO backup requirement of the PCI32
core, the FIFO usable buffer depth is the actual depth minus 3 words.
Data is loaded in the FIFO on each clock cycle that the write request is asserted and the address decode is valid. If
the transaction is not a burst, as when PLB_wrBurst is not high, and the PLB transfer is a single word or bytes within
a single word, a single PCI transaction (I/O or Memory Write command) is performed. In PLB burst transfers, as
when PLB_wrBurst is asserted, the data is buffered and the PCI transfer is initiated when the PLB write is
completed.
Only one PLB master write to a PCI target is supported at a time. Write transactions are not queued in the bridge.
After the PLB write to the bridge is completed and while a write to PCI is being completed, the PLBV46 PCI Bridge
asserts PLB rearbitrate to terminate subsequent PLB transactions. When a posted write is complete, another write
request from a PLB master can be initiated.
Consistent with the PCI specification, the PLBV46 PCI Bridge re-issues commands when an PCI retry is asserted. To
avoid permanent livelock, the posted write is attempted to be completed up to a predefined number of retries
defined by the parameter C_NUM_PCI_RETRIES_IN_WRITES.
Re-issuing the write operation on the PCI is automatic.
It is the responsibility of the master to properly write data to a PCI target from non-prefetchable PLB sources. For
example, it must perform single transaction reads of non-prefetchable PLB sources to avoid loss of data in
fire-and-forget writes to a PCI target.
The PLBV46 PCI Bridge does not support fast back-to-back PCI transactions.
Abnormal Terminations
In the context of the PLBV46 PCI Bridge, cacheline transactions are special cases of a burst. Abnormal terminations
during a cacheline write operation have the same response as a burst write transaction. Recall that the PLBV46 IPIF
specification requires that the targetword of a cacheline write be the first word of the line.
• If a SERR error, including a parity error during the address phase, is detected on either a single or burst
transfer, the PLB Master Write SERR interrupt is asserted. If the PLB transfer is in progress, Sl_MWrErr is
asserted with Sl_wrDAck.
• If on either a single or burst write the PLBV46 PCI Bridge asserts a master abort due to no response from a
target, the PLBV46 PCI Bridge asserts a PLB Master Write Master Abort interrupt. The IPIF2PCI FIFO is
flushed when the Master Abort Write interrupt is asserted. If the PLB transfer is in progress, Sl_MWrErr is
asserted with Sl_wrDAck.
• If on a single transfer or on the first data cycle of a burst transfer a PCI retry from the PCI target occurs, the
PLBV46 PCI Bridge automatically performs up to a parameterized number of retries. The number of retries is
set by C_NUM_PCI_RETRIES_IN_WRITES. A parameterized wait time before a retry occurs is set by
C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES. Both parameters are set at build time. During the time
retries are possible, subsequent PLB master write operations to a PCI target are inhibited by assertion of PLB
rearbitrate. If the retries are not successful, as when disconnects or more PCI retries occur, a PLB Master Write
interrupt identifying the failure mode is asserted. The IPIF2PCI FIFO is flushed upon asserting any of the three
PLB Master Write Retry interrupts. Consistent with the PCI Spec, the PLB master is required to perform the
write again if the last of the automatic retries was terminated with a PCI retry.
DS616 June 22, 2011
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Product Specification