DS616 Datasheet, PDF (40/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
• If on a single transfer the target disconnects with data, the transfer is completed.
• If the target disconnects, either with or without data after the first data phase of a burst transfer, the IPIF/PCI
core terminates the PCI transaction. If the IPIF2PCI FIFO is not empty, another PCI transaction is attempted.
Due to pipelining in the PCI core, the IPIF2PCI_FIFO must backup 1-3 words, depending on the type of target
disconnect. The PLBV46 PCI Bridge performs up to a parameterized number of retries
(C_NUM_PCI_RETRIES_IN_WRITES). A parameterized wait time
(C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES) before a retry occurs is included. Both parameters are
set at build time and are the same as defined for PCI retry situation. During the time retries are in progress,
subsequent PLB master write operations to a PCI target are inhibited. If the PCI transaction retries are not
successful due to any combination of PCI retries, disconnection, or time out, a PLB Master Write Retry
interrupt, PLB Master Write Retry Disconnect interrupt, or PLB Master Write Retry Timeout interrupt,
respectively, is asserted. The actual interrupt that is asserted is defined by the type of disconnect that occurred
on the last of the prescribed number of retries. The IPIF2PCI FIFO is flushed upon asserting one of the PLB
Master Write interrupts. Consistent with the PCI Spec, the PLB master is required to perform the write again if
the last of the automatic retries was terminated with a PCI retry.
• If on a single transfer or on a burst transfer a PERR error during data phase is detected, the PLBV46 PCI Bridge
aborts the PCI transaction and a PLB Master Write PERR interrupt is asserted. If the burst transfer is still in
progress, an Sl_MWrErr is asserted with Sl_wrDAck. The IPIF2PCI FIFO is flushed upon asserting the PERR
Write interrupt. The Detected Parity Error status register bit is set as well.
• If on a burst transfer the initiator latency timer expires, the PLBV46 PCI Bridge terminates the PCI transaction.
The PLBV46 PCI Bridge performs retries up to a parameterized number of times as described earlier for the
condition of disconnects with and without data. A time-out cannot occur during a single transfer because the
PCI32 core requires completion of one data transfer after the latency timer expires.
• If a target abort occurs during either a single or burst write operation, the PLB Master Write Target Abort
interrupt is asserted. If a burst write is in progress, Sl_MWrErr is asserted with Sl_wrDAck. Recall that a target
abort often indicates that the target cannot proceed with subsequent transactions; this is expected to be a major
failure most likely requiring a reset.
• If a PLB write request indicates a burst length that extends beyond the valid range of the IPIF BAR, as defined
by the C_IPIF_HIGHADDR_X parameter, the PLB Write Slave BAR Overrun interrupt is asserted. The PLBV46
PCI Bridge does not initiate a write on the PCI bus even though it responds to the PLB Master with
Sl_wrDAck.
DS616 June 22, 2011
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Product Specification