DS616 Datasheet, PDF (25/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Device Interrupt Enable Register (IER)
The Device Interrupt Enable Register determines which interrupt sources in the Device Interrupt Status Register are
allowed to generate interrupts to the system. The bits are detailed in Table 9.
Table 9: Device Interrupt Enable Register (DIER) Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access Reset Value
Description
0-28
I
Read
0x0
Unassigned (not writable)
29
BIRE
Read/Write
0x0
Bridge Interrupt Request Enable. This bit is the interrupt enable
for the BIR bit in the DISR.
• ’0’ = Mask Interrupt.
• ’1’ = Enable Interrupt.
30
DPTOE
Read/Write
0x0
Data Phase Time-out Enable. This bit is the interrupt enable for
the DPTO bit in the DISR.
• ’0’ = Mask Interrupt.
• ’1’ = Enable Interrupt.
31
TERRE
Read/Write
0x0
Transaction Error Enable. This bit is the interrupt enable for the
TERR bit in the DISR.
• ’0’ = Mask Interrupt.
• ’1’ = Enable Interrupt.
Device Interrupt ID (IID)
The Device Interrupt ID Register is an ordinal value output of a priority encoder. The value indicates which
interrupt source, if any, has a pending interrupt. A value of 0x80 indicates that there are no pending interrupts,
otherwise, the value gives the bit position in the DIPR of the highest priority interrupt that is pending.
The priority is highest for the interrupt bit in the LSB position (bit 31), which reports as ID value 0x00, and decreases
in priority (and increases in the reported ID value) for each successively more significant position, such as going
left. The bits are detailed in Table 10.
Table 10: Device Interrupt ID Register (DIIDR) Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
0-23
24-31
Name
IID
Access
Read
Read
Reset Value
Description
0x0
Unassigned
0x80
Interrupt ID.
• 0x80 - The DIPR has no pending interrupts.
• Otherwise - The ordinal ID of the highest-priority
pending interrupt in the DIPR.
DS616 June 22, 2011
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Product Specification