DS616 Datasheet, PDF (24/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 7: Device Interrupt Status Register (DISR) Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access Reset Value
Description
0-28
I
Read
0x0
Unassigned
29
BIR
Read/TOW
0x0
Bridge Interrupt Request. This interrupt indicates that the
Bridge interrupt input on the IPIF input has been captured in the
Bridge Interrupt Status Register and is enabled via the Bridge
Interrupt Enable Register.
• ’0’ = No enabled interrupt is captured
• ’1’ = Bridge interrupt is captured and enabled.
30
DPTO
Read/TOW
0x0
Data Phase Time-out. This interrupt indicates that a Data Phase
time-out occurred during a Read or Write transaction request.
The time-out value (PLB clocks) is set to 255 clock periods.
• ’0’ = No Time-out detected.
• ’1’ = Data phase Time-out detected.
31
TERR
Read/TOW
0x0
Transaction Error. This interrupt indicates that a function within
the Bridge (not IPIF timeout) responded to a Read or Write
transaction request with the assertion of the Slv_MErr signal.
• ’0’ = No transaction error detected.
• ’1’ = Transaction Error detected.
Device Interrupt Pending Register (IPR)
The Device Interrupt Pending Register is a read-only value that is the logical AND of the Device Interrupt Status
Register and the Device Interrupt Enable Register (see Table 8) on a bit-by-bit basis. The bits are detailed in Table 8.
Therefore, the Interrupt Pending Register only reports captured interrupts that are also enabled by the
corresponding bit in the Interrupt Enable Register.
Table 8: Device Interrupt Pending Register (DIPR) Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s)
Name
Access Reset Value
Description
0-28
I
Read
0x0
Unassigned
29
BIRP
Read
0x0
Bridge Interrupt Pending. This bit is the logical ’AND’ of the
Bridge IR bit in the DISR and the corresponding bit in the DIER.
• ’0’ = No Bridge interrupt pending
• ’1’ = Bridge interrupt is pending.
30
DPTOP
Read
0x0
Data Phase Time-out Pending. This bit is the logical ’AND’ of the
DPTO bit in the DISR and the corresponding bit in the DIER
• ’0’ = No Time-out interrupt pending.
• ’1’ = Time-out captured and enabled.
31
TERRP
Read
0x0
Transaction Error Pending. This bit is the logical ’AND’ of the
TERR bit in the DISR and the corresponding bit in the DIER
• ’0’ = No transaction error pending.
• ’1’ = Transaction Error captured and enabled.
DS616 June 22, 2011
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24
Product Specification