DS616 Datasheet, PDF (38/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Table 21 summarizes the abnormal conditions with which a PCI target can respond and how the response is
translated to the PLB master.
Table 21: Response of PLB Master/v3.0 Initiator read of a remote PCI target with abnormal condition on
PCI bus
Abnormal Condition
Single Transfer
Burst
(PLB_rdBurst asserted)
SERR (includes parity error on
address phase)
PLB Master Read SERR interrupt
PLB Master Read SERR interrupt
asserted. Data is discarded. Sl_MRdErr is asserted. Data is discarded. Sl_MRdErr is
asserted.
asserted.
PLBV46 PCI Bridge Master abort
(no PCI target response)
Prefetch abandoned. Sl_MRdErr is
asserted.
Prefetch abandoned. Sl_MRdErr is
asserted.
Target disconnect without data (PCI Immediate automatic retry
Retry)
Immediate automatic retry
Target disconnect without data (after N/A
one completed data phase)
Target disconnect with data
Completes
Data is being buffered in PLBV46 PCI
Bridge PCI2IPIF FIFO. The PCI transaction
is terminated by the disconnect. If the
encoded length has not been prefetched,
the PLBV46 PCI Bridge issues another PCI
transaction at correct address. If a PCI retry
is asserted, the PCI read automatically
retried.
PERR
Data is transferred and the PLB Master
Read PERR interrupt asserted
PLB Master Read PERR interrupt is
asserted and any data is discarded
Latency timer expiration
N/A because the PCI32 core waits for one Same as target disconnect with/without
transfer after timeout occurs
data
Target Abort
The PLB Target Abort Master Read
The PLB Target Abort Master Read
interrupt asserted. Sl_MRdErr is asserted. interrupt asserted and any data is
discarded. Sl_MRdErr is asserted.
Address increments beyond valid N/A
range
Stop PCI transaction. Assert PLB Read
Slave BAR Overrun interrupt and assert
Sl_MRdErr with Sl_rdDAck to PLB master.
PLB Master Initiates a Write Request to a PCI Target
This section discusses the operation of an PLB master initiating single, burst and cache line write transactions to a
remote PCI target. All PLB write transactions are posted-writes. Because both single PLB writes and burst PLB
writes to the bridge are fire-and-forget, any error in completing the write occurs mostly likely after the PLB
transaction is completed. The errors are signaled by an interrupt when an incomplete PCI transactions occur or
when PCI errors occur. Details of the abnormal terminations are discussed in a later section. In these transactions,
the PCI32 core is the PCI initiator.
The operation is essentially the same whether the PCI space is memory or I/O space; the only difference is the
command sent to the PCI32 core by the PLBV46 PCI Bridge. The bridge can accept only fixed length burst
transactions on the PLB. All PLB burst transfers are 32-bits per data phase; dynamic byte enable is not supported by
the PLB protocol. The PLB specification requires all cacheline write transactions to be sequential fill type,
independent of the target word; however, the PLBV46 IPIF requires the address received during a cacheline write
operation to be the first word of the line being written.
Commands supported in PLB master write operations are I/O write and memory write (both single and burst). The
command used is based on the address/qualifier decode, which includes the address, memory type, such as I/O or
memory type, and if PLB_wrBurst is asserted. Table 19 shows translations of PLB transactions to PCI commands.
DS616 June 22, 2011
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Product Specification