DS616 Datasheet, PDF (44/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
All memory write commands are posted, with error notification mostly likely occurring after the PCI transaction
with the bridge has completed. The main reason for posted operation is that the PCI32 core does not permit data
throttling by the PLBV46 PCI Bridge to utilize PLB burst write commands without buffering data. It is desirable to
utilize the PLB burst write command when possible to increase data throughput.
To utilize burst write PLB transactions, data is buffered in the IPIF master PCI2IPIF FIFO until either the PCI write
operation terminates or until the PCI2IPIF FIFO is full. If C, the data are burst written over the PLB until the FIFO
is emptied, which can take multiple transactions if the PLB slave terminates the transaction. If the PCI write is
terminated before the PCI2IPIF FIFO is full, the IPIF master burst writes starts after the PCI transaction ends. The
bridge attempts to burst write all the data to the PLB slave device.
Although dynamic byte enable is supported on the PCI bus, dynamic byte enable is not supported by the PLBV46
PCI Bridge because the PLB protocol requires all byte enables to be asserted during burst writes on the PLB. It is the
responsibility of the user to ensure that all byte enables be asserted on the PCI in burst write operations to the
PLBV46 PCI Bridge.
A PCI initiator can write any number of words of data in a burst operation to the PLBV46 PCI Bridge and the bridge
attempts to burst the data to the PLB slave in a burst write operation on the PLB. The slave can terminate the PLB
burst or the FIFO can empty because the FIFO is not filled as fast as the data is transmitted over the PLB.
The PLBV46 PCI Bridge can accept a PCI initiator write while a read prefetch is in process. However, only one PCI
initiator write to a PLB slave is supported at a time. It is possible for the PLBV46 PCI Bridge to be completing a
posted write operation when another write command is received. When this happens, the PLBV46 PCI Bridge
forces the PCI to disconnect without data until the posted write operation to a remote PLB slave has completed.
A write to a remote slave that is terminated before the FIFO is emptied is automatically retried by the PLB/PCI
bridge. Address bookkeeping is performed in the IPIF to permit the correct sequence of PLB transactions as either
bursts or single transactions and/or combinations of the two as required to complete the transfer.
Abnormal Terminations
• If an address parity error is detected, the PCI32 core will either claim the transaction and issue a target abort, or
will not claim the transaction and a master abort will occur (see PCI32 core documentation). If enabled, the
PCI32 core asserts SERR_N when address phase parity errors are detected.
• If SERR_N is asserted by a remote agent in a data phase, the bridge disconnects without data for burst
transfers and the PLB-side PCI Initiator Write SERR interrupt is asserted. If the SERR occurs after the IP master
device has started a PLB transaction, the PLB transaction is terminated as soon as possible. The PLBV46 PCI
Bridge flushes any data and resets for a subsequent transaction. It is left to the PCI initiator to report the error
on the PCI-side and initiate any recovery effort that may be needed.
• If a PERR error is detected on a write transfer, the PCI32 core asserts the PERR signal, if enabled, and sets the
Detected PERR error in the status register. The PLBV46 PCI Bridge disconnects without data for burst
transfers. On the PLB-side, the bridge terminates the PLB transfer as soon as possible if the transaction is in
progress. Due to the latency in PERR, the data for which the PERR was detected most likely has been written
to the PLB slave. It is left to the PCI initiator to report the error and initiate any recovery effort that may be
needed.
• If at any time while data from the PCI2PLB_FIFO is being written to a PLB slave, a PLB rearbitrate occurs, the
PLBV46 PCI Bridge performs write retries until successful, or the limit of 2028 retries is reached. If the limit is
reached, the PLB Master Write Rearb Timeout interrupt is asserted. The PLBV46 PCI Bridge IP master write
state machine is tied up during the retry operation, therefore, PCI initiator writes are inhibited. Target
disconnects without data (PCI retry) are asserted for subsequent PCI transactions when the transactions are
inhibited.
DS616 June 22, 2011
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Product Specification