DS616 Datasheet, PDF (55/60 Pages) Xilinx, Inc – LogiCORE IP PLBV46 PCI Full

LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a)
Other constraints that are required include the IOBDELAY_TYPE, IOBDELAY_VALUE and IOB. These parameters
are set in the normal EDK tool flow, but can be included in the system top-level UCF. For alternative tool flows, the
setting are shown in the Virtex-4 Only Constraints example. The settings shown are settings at the time this
document was written. The LogiCORE IP v3 PCI32 core Implementation Guide and v3.0 core ucf generator tool should
be checked for updated values. IOSTANDARD must be explicitly defined in the UCF with the BYPASS constraint
for ISE 8.1 tools; this can change in with future versions of the tools.
#-------------------------------------------------------------------------
# Virtex-4 Only Constraints
#-------------------------------------------------------------------------
INST "*XPCI_CBD*"
IOBDELAY_TYPE=VARIABLE ;
INST "*XPCI_ADD*"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_PARD"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_FRAMED"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_TRDYD"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_IRDYD"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_STOPD"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_DEVSELD" IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_PERRD"
IOBDELAY_TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_SERRD"
IOBDELAY_TYPE=VARIABLE ;
#Include next 2 if routed to pins
INST "*XPCI_IDSEL"
IOBDELAY_TYPE=VARIABLE ;
INST "*XPCI_GNTD"
IOBDELAY_TYPE=VARIABLE ;
INST "*XPCI_CBD*"
IOBDELAY_VALUE=55 ;
INST "*XPCI_ADD*"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_PARD"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_FRAMED"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_TRDYD"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_IRDYD"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_STOPD"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_DEVSELD" IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_PERRD"
IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_SERRD"
IOBDELAY_VALUE=55 ;
#Include next 2 if routed to pins
INST "*XPCI_IDSEL"
IOBDELAY_VALUE=55 ;
INST "*XPCI_GNTD"
IOBDELAY_VALUE=55 ;
Some of the Virtex-4 FPGA constraints are implemented automatically in the EDK tool flow with any tool option
that invokes bridge synthesis. As described earlier, TCL scripts generate the UCF constraints and place them in a
file in the PLBV46 PCI Bridge directory of the project implementation directory. The UCF constraints are then
included in the NGC file generated in the EDK tool flow. The user can check the UCF in the implementation
directory of the bridge directory to verify that the constraints are included. Alternatively, the user can include all
constraints in the top-level UCF. When the constraints are included in both the top-level UCF and the bridge NGC
file (via the bridge directory UCF), then the top-level UCF overrides any conflicting constraints in the bridge NGC
file.
DS616 June 22, 2011
www.xilinx.com
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Product Specification